In the conventional photolithographic processing of integrated circuits, features are created on a semiconductor wafer by exposing the wafer with light or radiation that is passed through a mask or reticle. A typical mask/reticle has patterns of opaque and clear areas that selectively expose corresponding areas of light-sensitive chemicals on the wafer. The exposed areas are chemically and mechanically processed to create the desired features on the wafer.
As the size of features being created on a wafer approaches and becomes smaller than the wavelength of radiation used to expose the wafer, optical distortions can occur whereby the pattern defined on the mask or reticle will not match the pattern of features that are created on the wafer. To improve the pattern fidelity, changes can be made to the mask/reticle patterns that compensate for the expected optical distortions. One common tool for adjusting the mask/reticle pattern is an optical and process correction (OPC) tool such as the CALIBRE® software tools available from Mentor Graphics Corporation, the assignee of the present invention.
As will be appreciated by those skilled in the art, an OPC tool works to produce a corrected mask/reticle by reading at least a portion of a layout design that is defined in a database. Each feature to be created on the wafer is defined as a series of vertices that make up a polygon having a shape of the desired feature. The polygons are fragmented by dividing the perimeter of the polygon into a plurality of edge fragments. An edge placement error (EPE) is computed for each edge fragment that compares where an edge fragment will be printed on a wafer versus its desired position. The OPC tool then moves the edge fragments in order to precompensate for the expected optical distortions that will occur during processing so that the position of the edges created on a wafer will more closely match the desired positions.
FIG. 1A illustrates a representative polygon 1 that defines a rectangular feature to be created on a wafer. In order to correct for optical distortions, the polygon 1 is divided into a plurality of edge fragments that are bounded by fragmentation end points 12. During OPC, at least some of the edge fragments positioned between the fragmentation end points 12 are moved inwardly or outwardly to compensate for optical distortions. In the example shown in FIG. 1A, the polygon 1 does not contain a sufficient number of fragmentation points 12 to create the rectangular feature on the wafer with an acceptable image fidelity. A simulated aerial image 14 plots where the edge fragments will be printed on a wafer. In the example shown, the fragmentation of the polygon 1 is too coarse in order to be able to finely correct for the optical distortions that may occur during processing. Conversely, FIG. 1C illustrates a polygon 1 including more than enough fragmentation end points 12 to finely adjust for the optical distortions that may occur during processing. Although the number of fragmentation end points 12 is sufficient in the example shown in FIG. 1C, the time required to compute the OPC corrections of each individual edge fragment may be prohibitive. Therefore, it is desirable to divide the polygon 1 in a manner as shown in FIG. 1B with a sufficient number of fragmentation end points 12 so that image fidelity is acceptable and processing time is not prohibitive.
Associated with each edge fragment is a simulation site that defines a number of sample points at which the image intensity during photolithographic processing is estimated. From the estimated image intensity points, a determination is made of the expected edge placement error (EPE) of the edge fragment. FIG. 2 shows a conventional, simplistic method of placing the simulation sites on the edge fragments. Simulation sites 16a are placed in the center of the edge fragments that are at the ends of the polygon and simulation sites 16b are positioned at the location of the fragmentation end points 12 that are adjacent to the corners of the polygon. Additional simulation sites 16c are placed in the center of the edge fragments that are between the fragmentation end points 12 for the remainder of the polygon. Comparing the location of the simulation sites with simulated aerial image 18 (which is a plot of the estimated image intensity at a value that will expose the chemicals on the wafer), it can be seen that many simulation sites are not positioned at the place where the aerial image intensity deviates most significantly from the desired outline of the polygon 1. Therefore, if OPC corrections are made based on the location of the simulation sites as originally positioned, the most optimum edge correction will likely not be achieved.
To achieve improved OPC corrections, it is desirable to place the simulation sites and/or use varying numbers of simulation sites at positions closer to where the EPE of an edge fragment is greatest along the length of an edge fragment.